Reseeding methodology for low power based on LFSR

Power dissipation during test is a significant problem as the size and complexity of systems-onchip (SOCs) continue to grow. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation. This problem is further pseudorandom filling of the unassigned input values is employed. Excessive power dissipation during test can increase manufacturing costs by requiring the use of a more expensive chip packaging or causing unnecessary yield loss. The proposed encoding scheme can be used in conjunction with any lfsr-reseeding scheme to significantly reduce test power and even further reduce test storage is presented. Experimental results show that the proposed scheme can significantly reduce the power dissipation. Keywords— test-data compression, test power,